MyHDL is a python based HDL language developed by Jan Decaluwe. Here we will talk about how to write code in MyHDL.
For purpose of simplicity we will try to create FIFO and its test bench.
What is FIFO?
FIFO is an acronym for first in, first out, a method for organizing and manipulating a data buffer, where the oldest (first) entry, or ‘head’ of the queue, is processed first. It is analogous to processing a queue with first-come, first-served (FCFS) behaviour: where the people leave the queue in the order in which they arrive. curtsy wikipedia
So lets talk about interface signals for a FIFO module.
Half full FIFO model
clk : input signal for clock
inbusy : input bus is busy
we : input bus write enable
din : input bus data input
outbusy: output bus is busy
rd : output bus read enable
dout : output bus data output
rdout : output bus data valid
rst : input reset
These are the obvious signals one should have in the FIFO module. “inbusy” and “outbusy” signals are important in order to signal master that the buffer overflow or underflow event has occured.
Here @block represents module in HDL. And instances() return all the instences defined in the module. Presently no instances are defined.
Lets define some memory for fifo. Here “DATA” is the bus width for the mem register array and “2**ADDR” is the count of total such registers.
Lets define some signals. “in_addr” and “out_addr” are two pointer signals which points to the present memory address for the corresponding input and output buses.
Now lets write some instances. “@always_seq(clk.posedge, reset = rst)” emplies a sequential instance where event trigers on positive clock edge. Further all registers gets reset to their initial values on reset event.
Write Logic instances
Read Logic instances
In order to avoid buffer overflow and underflow events we have to take care of the gap between “in_addr” and “out_addr”
Let us see the complete code
In order to write a test bench we will use a puthon’s unit test framework. In order to use this frame work we will write a testcase class.
At first lets write a skelton class “TestFifo” which actually does noting.
On running the test output is as follows.
Now lets populate the test bench. “createbuff” creates a test buffer that we will write to the fifo later.
Now here again “@block” we are defining a test bench module to test fifo. Various signals have been defined. “fifo_inst” that is device under test, also defined here.
“fifo_inst.convert” converts fifo MyHDL model to the verilog.
Lets generate “clk” and “rst” logic signals.
Lets logic for writing to and reading from fifo.
Here is the complete code for test bench.
here is the output while execution of the test bench.
It also generates signal traces that we can see by reading generated *.vcd file in gtkwave.